Regarding electronic devices, particularly battery-operated hand-held devices that utilize a processor, the issue of power consumption is a concern that is considered during the design phase of the device. Since a processor's clock typically consumes a relatively large amount of battery power, it is well known to design the electronic devices such that the clock can be shut off during extended periods of inactivity. Prior to stopping the clock, however, power management logic usually requests that the processor enter an “idle” state in which the processor does not perform further bus accesses or other processing operations. When the processor is idle, the power management logic can then safely stop the clock.
Not only does shutting down the clock conserve battery power, but it also allows heat to be properly dissipated from the electronic device. Since a processor often operates on non-critical instructions, such as “loop to self” instructions, it may be beneficial to design a device with processor idling circuitry to avoid unnecessary processor usage that will invariably produce heat. In some cases, cutting unnecessary usage time can reduce the production of heat to such a degree that the device can be designed to operate without the use of a fan, thereby allowing the size and cost of a device to be reduced. Also, with adequate heat dissipation, hand-held devices are less likely to overheat or become too warm to the touch. Another advantage in this regard is that less expensive packaging may be used when heat is properly controlled.
FIG. 1 illustrates a conventional processing system 10 of an electronic device, such as a battery-operated hand-held device. The processing system 10 includes power management logic 12, a processor 14, memory 16, and input/output devices 18, each interconnected via an internal bus 20. The processor 14 includes a clock 22 for driving the electrical circuitry as is well known. The memory 16 may include a memory controller and other hardware and/or software elements. The input/output devices 18 may include keyboards, keypads, display screens, etc. Since one of ordinary skill in the art will understand the operation and function of the memory 16 and input/output devices 18, these components will not be further described in this disclosure.
The power management logic 12 may include hardware and/or software elements for determining specific circuit conditions that might be ideal times when automatic power-saving measures can be taken. For example, the power management logic 12 may monitor when the processor has not been working on any critical instructions for a predetermined length of time or monitor periods of user inactivity or other specific circuit conditions. In these situations, the power management logic 12 can request that the processor 14 go to an idle condition. When the processor 14 is idle, the power management logic 12 can then disable the processor's clock 22. Later, when a wake-up event occurs, the power management logic can re-enable the clock 22.
FIG. 2 illustrates an embodiment of a conventional processor 14. The processor 14 contains a processor pipeline 24 configured in five stages, each stage uniquely handling the processing of data and interacting with the memory 16 and/or input/output devices 18 as needed. The stages of the pipeline 24 include a fetch stage 26, a decode stage 28, an execute stage 30, a memory access stage 32, and a write-back stage 34. Although a processor typically might have five stages representing five major operations of the processor, the stages can be divided or regrouped into any desirable configuration. It is well known in the art that other conventional processors may have fewer or more stages in its pipeline.
FIG. 2 also shows the processor's clock 22 connected to each stage of the pipeline 24 for feeding clock signals thereto. The clock 22 is also connected to receive an enable/disable signal from the power management logic 12. The processor 14 also contains an AND gate 36 having inputs connected to receive an “idle” signal from each stage and an output that feeds an “idle_acknowledge” signal back to the power management logic 12. In the fetch stage 26, an AND gate 38 is configured having a first input receiving an “idle_request” signal from the power management logic 12 and a second input receiving normal instruction requests along line 40 from within the fetch stage 26.
It should also be noted that each stage includes idle detection circuitry (not shown), which is unique to that stage for determining when the stage is idle. Once the idle detection circuitry of the fetch stage 26, for example, detects an idle condition when there are no instructions to fetch, it will send a high “idle” signal to one of the inputs of the AND gate 36. Also, the idle detection circuitry in each of the decode stage 28, execute stage 30, memory access stage 32, and write-back stage 34 will also eventually detect that they too are idle and independently send idle signals to the AND gate 36 as well. When idle signals are received from each stage, the AND gate 36 outputs a logic 1 idle_acknowledge signal. When the power management logic 12 receives the idle_acknowledge signal, it can then send a disable signal to the clock 22 to shut it down.
During normal operation of the processor 14, the power management logic 12 maintains the idle_request signal inactive (logic 0). The first input of the AND gate 38 inverts the inactive idle_request signal, i.e. not idle, and the second input receives the normal instruction requests from line 40. With idle_request inactive, the AND gate 38 outputs the normal instruction request along line 42 to fetch an instruction from memory 16. In response to a request for instructions, the memory 16 returns instruction values, e.g. from a software program, along line 44 back to the fetch stage 26. The fetched instruction values are sent to the decode stage 28, which decodes the signals and sends the decoded instructions to the execute stage 30. The execute stage 30 performs the instructions, and the memory access stage 32 and write-back stage 34 can read data from or write date to memory 16 and/or register files as necessary.
In order to conserve power during periods of inactivity, the power management logic 12 may decide to stop the clock 22, which, as mentioned above, requires that the processor stages be inactive or idle. To idle the processor, the power management logic 12 sends an active or high (logic 1) idle_request signal to the processor 14 to stop the fetch stage 26 from making more instruction fetch requests. The idle_request signal essentially disables the normal instruction requests along line 40 from being output from the AND gate 38. Consequently, requests for instructions are momentarily discontinued. It should be pointed out, however, that outstanding instruction requests, which may have been sent out from the processor 14 immediately before the idle_request was received, may still be traversing to or from memory 16. Because of this, the fetch stage 26 may still receive additional instruction values from memory 16 several clock cycles after receiving the idle_request signal. Eventually, however, the memory 16 will stop sending instruction values. At some time thereafter, idle detection circuitry of the fetch stage 26 will detect that no instructions are being received and will send out an idle signal to AND gate 36. The idle detection circuitry in the following stage will also eventually detect inactivity and likewise send an idle signal.
A disadvantage of the prior art approach to idling a processor pipeline is that each stage must decode its own idle state uniquely and as a result there is no consistency in the design of this feature in each processor pipeline stage. The lack of consistency adds to the risk of making a mistake in the design of the processor. For instance, the execute stage must include logic to detect that each of its parts, e.g. multiplier, arithmetic unit, add/subtract unit, shifter, logical unit, etc., are all idle to determine if the whole stage is idle. If the designer of the execute stage accidentally designs the idle detection circuitry without checking one of these parts, then a circuit condition that should rightly indicate activity may be missed. Just one of a multitude of possible idle conditions not being accounted for could result in an improper processor idle indication. With many circuit conditions to consider in order to idle the processor, the chances of design error will only increase as processor complexity increases. Therefore, a need exists to simplify the processor idle detection circuitry to provide a more consistent approach for idling the processor.